In the post-Moore era, high-performance computing technologies are increasingly demanding high-efficiency and energy-saving chipsets through advanced packaging technologies. At present, system-in-package (SiP) has become the most mainstream packaging solution in the field of high-performance computing. Among them, Chiplet technology and 2.5D/3D packaging have rapidly emerged and become the technological trend of high-performance computing applications. JCET provides a series of packaging and testing solutions for high-performance computing, covering wire bond packaging, flip-chip packaging, wafer-level packaging (WLP), and system-in-package (SiP). JCET’s unique XDFOI technology, as an ultra-high-density TSV-less fan-out packaging technology, can support the integration of multiple chips, high bandwidth memory (HBM), and passive components to achieve better performance and reliability while optimizing costs.

  • Artificial Intelligence
  • Data Center
  •  Blockchain 

Our Advantages

Cost-Effective 2.5D Package

Ultra High-Density Bumping

Complete Flip-Chip Portfolio

HVM-Proven WLP Solutions

Experienced in Crypto ASICs

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